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Work with architects, logic designers, and ASIC vendors to drive architectural feasibility studies, develop timing and design targets, and explore RTL/design tradeoffs for physical design closure.
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Work with logic verification and software teams to understand and implement the design requirements for clocking and power management.
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Competencies
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Experience setting flows and methodologies for physical design and design sign off.
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Hands-on experience in each of the following physical design flows and methodologies: synthesis, place and route, STA, formal verification, CDC and power/EM/IR analysis, power intent (UPF/CPF), DFT.
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Hands-on experience and a solid understanding in most or all of the following tools: Design Compiler, ICC/ICC2, Innovus/EDI, Primetime, Conformal LEC and CLP, Spyglass and Power Artist, DRC tools such as Calibre, DFT Compiler/Tessent/Encounter Test, Electrical Analysis tools such as Redhawk/Voltus.
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Proficiency in semiconductor device physics and transistor characteristics.
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