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Develop all aspects of Field Programmable Gate Array implementation (design partitioning, synthesis, place and route, timing analysis, third-party IP integration, RTL simulation, and debugging).
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Drive block and full-chip level FPGA implementation and FPGA QoR (timing, capacity).
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FPGA implementation, platform bringup, digital design, SoC architecture, common bus interfaces such as AMBA family, common IO's such as PCIe, MIPI, USB, IC2, and JTAG, verification, waveforms.
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Experience with Linux operating systems and experience in IP integration on FPGA (memories, flash, cameras, IO, and analog IP).
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Experience debugging system-level software/comfortable debugging across the stack. Strong programming skills in C/C++ and scripting skills in Python, Tcl, and/or Perl.
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Experience and/or knowledge in Verilog generators and high level synthesis (HLS).
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