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Develop all aspects of Application Specific Integrated Circuit implementation with emphasis on physical synthesis, place and route, and static timing analysis.
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Manage block and full-chip level physical implementation and QoR (power, timing, area).
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1 year of experience in ASIC physical design flows and methodologies in 7nm-40nm process nodes.
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Experience and/or knowledge of high level synthesis (HLS).
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Experience in IP integration (memories, FLASH, IO and Analog IP).
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Experience in extraction of design parameters, QoR metrics, and analyzing trends.
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Knowledge of semiconductor device physics, transistor characteristics, and multiple foundry.
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